A CMOS AGC-less IF Strip for Bluetooth

This paper presents an IF chain suitable for Low-IF fully-integrated GFSK receivers. The circuit performs amplification and channel selection (including image rejection). A five-pole Gm-C polyphase filter forms the core of the IF strip. The filter is current driven and has transimpedance gain of ≃ 120 kΩ. The filter is architectured so that GFSK signals with dynamic range exceeding 50dB can be decoded without the need of any automatic gain control. This AGC-less IF strip was fabricated in standard 0.25 µm CMOS process. It draws 6.2 mA from a 2.5 V supply and has better than 4.8 nA rms input referred noise. Input signals (compliant with Bluetooth) were applied and the output signal was collected for software decoding . Generated BER plots meet Bluetooth specifications

A Robust 43-GHz VCO in CMOS for OC-768 SONET Applications

In this paper, we present a 43-GHz LC-VCO in 0.13-/spl mu/m CMOS for use in SONET OC-768 optical networks. A tuned output buffer is used to provide 1.3 V/sub p-p/ (single-ended) into a 90-fF capacitive load as is required when the VCO is used in typical clock and data recovery (CDR) circuits. Phase noise is -90 dBc/Hz at a 1-MHz offset from the carrier; this meets SONET jitter specifications. The design has a tune range of 4.2%. The VCO, including output buffers, consumes 14 mA from a 1-V supply and occupies 0.06 mm/sup 2/ of die area. Modern CMOS process characteristics and the high center frequency of this design mean that the tank loss is not dominated by the integrated inductor, but rather by the tank capacitance. An area-efficient inductor design that does not require any optimization is used

2-Diphenylphosphinomethyl-3-methylpyrazine

The lateral metalation-electrophilic trapping reaction of alkyl-substituted pyrazines has always been challenging and poorly regioselective, with the corresponding derivatives often being isolated in moderate yield. In this contribution, we first report on the preparation of an unsymmetrically-substituted pyrazine, that is 2-diphenylphosphinomethyl-3-methylpyrazine, by subjecting to metalation with n-BuLi the commercially available 2,3-dimethylpyrazine, followed by interception of the putative lithiated benzyl-type intermediate with Ph2PCl. Such a functionalization has been successfully carried out in the absence of additional ligands, working either in THF at −78 °C or in a more environmentally friendly solvent like cyclopentyl methyl ether at 0 °C, with the desired phosphine derivative being isolated in 70–85% yield. The newly synthesized adduct has been fully characterized by means of multinuclear magnetic resonance spectroscopic techniques, and also by preparing a selenium derivative, which furnished single crystals that were suitable for X-ray analysis

7V Tristate-Capable Output Buffer Implemented in Standard 2.5V CMOS Process

This paper describes high-voltage CMOS buffer architecture that uses low-voltage transistors. The voltage capability of the presented architecture is nearly three times larger than the voltage capability of the used MOSFET\u27s. This buffer topology could be used to provide 3.3 V compatibility of 1.2 V and 1.5 V digital ICs implemented in standard CMOS technology. A 7 V circuit-prototype was fabricated in 0.25 /spl μ/m 2.5 V CMOS technology. Performed measurements demonstrate stress-free operationin both active and high-impedance mode

A Divide and Conquer Technique for Implementing Wide Dynamic Range Continuous-Time Filters

This paper presents a technique for implementing analog filters with wide dynamic range and low power dissipation and chip area. The desired dynamic range of the filter is divided into subranges, each covered by a different filtering path optimized specifically for this subrange. This results in small admittance levels for the individual filtering paths and correspondingly small power dissipation and chip area. The system provides undisturbed output during range switching, contrary to conventional automatic gain control (AGC)/filter arrangements that generate disturbances every time the gain of the AGC changes. We also report on a low-noise highly linear CMOS transconductor useful for high-frequency applications. A chip implementing the ideas of this paper was fabricated in a 0.25-μm digital CMOS process. The intended application of the filter is channel selection in an 802.11a/Hiperlan2 Wireless Ethernet receiver. The chip dissipates 9 mA, occupies an area of 0.7 mm2 , and maintains a signal/(noise+ IM3 distortion) ratio of at least 33 dB over a 48-dB signal range, with good blocker immunity. This performance represents at least an order of magnitude improvement over existing channel selection filters, even those that do not achieve disturbance-free operation

Testing the Double Low-IF Receiver Architecture

The purpose of this paper is to show through laboratory results, the performance of the new DLIF (Double Low-IF) receiver architecture. This new approach minimizes the receiver's cost by eliminating the need for RF image-reject and IF-Saw channel filters, avoids some of the shortcomings of direct conversion and single Low-IF methods and can be applied in GSM-like mobile stations. Performance results are presented in terms of Frame Error Rates and Residual Bit Error Rates and can thus be compared with GSM specifications. I INTRODUCTION In this paper detailed test results are provided for an implementation of the Double Low-IF receiver architecture [1] in GSMlike systems. On one hand the tests include classical tests like noise figures, compression points, power consumption etc. On the other hand, we embedded the DLIF chip into a loop-back test configuration using Lucent Sceptre-I baseband components to obtain performance results in terms of frame error rates (FER) and residual bit er..

Stable High-Order Delta-Sigma DACs

Stability analysis of high-order delta-sigma loops is a challenge. In this brief, a sufficient design criterion is presented for highorder multibit error-feedback DACs which are especially suitable for high-speed operation. This analytical criterion might be too conservative, but it allows the design of stable, robust, and high-resolution deltasigma DACs. Both analytical and numerical analysis are performed for verification. Also, experimental results of a discrete-component multiplier-free prototype demonstrate 10-bit operation at a very low oversampling ratio of 4

A low phase noise 5GHz Quadrature CMOS VCO using common mode inductive coupling

A new concept for quadrature coupling of LC oscillators is introduced and demonstrated on a 5GHz CMOS VCO. It uses injection-locking through commonmode inductive coupling to enforce quadrature. The technique provides quadrature over a wide tuning range without introducing any phase noise- or power consumption increase. The realized VCO is tunable between 4.6GHz and 5.2GHz and measures a phase noise lower than -124dBc/Hz at 1MHz offset over the entire tuning range. The circuit draws 8.75mA from a 2.5V supptv

A 32-mW 320-MHz Continuous-Time Complex Delta-Sigma ADC for Multi-Mode Wireless-LAN Receivers

We present an experimental continuous-time complex delta-sigma multi-bit modulator, implemented in standard 0.25-μm CMOS technology and meeting all major requirements for application in IEEE 802.11a/b/g wireless LAN receivers. The clock frequency is 320 MHz, producing an oversampling ratio of 16 for 20 MHz channel bandwidths. The modulator supports two operation modes for zero-IF and low-IF receiver architectures respectively, requires a single 2.5-V power supply, and dissipates only 32 mW of power. The measured peak signal-to-noise ratio is 55 dB. Further experimental results using sine-wave and OFDM test signals are also presente